This invention relates to the fields of electronic computing hardware and software and communications, and is more specifically directed to improved circuits, devices, and systems for information and communication processing, and processes of operating and making them. Branch prediction can improve performance of branch instructions in a high-performance processor system. Branch prediction improves the efficiency and effectiveness of the instruction fetch process and confers an acceleration to running code without additional software cost. Running code is accelerated by keeping a pipeline full in a microprocessor that has a pipeline. Also, acceleration is facilitated by buffering and hiding all or part of instruction fetch latency (cache and other memory access cycles consumed by instruction fetch) by parallelizing instruction fetch of later instructions with decode and execute operations for earlier instructions in the flow.
In some specific use cases, branch prediction has undesirable side-effects. Sometimes, branch prediction can do harm at a point a branch instruction is branch-predicted when the user program is running. It is desirable in the art to provide ways of avoiding problems with branch prediction.